MPEG Architect/Designer

Job Description Contribute to architecture definition of next-generation of advanced Digital TV SOCLead architecture definition and implementation of multi-standard MPEG decoder Lead requirements analysis, HW/SW partitioning, architecture and microarchitecture development of high definition and low bit-rate video decode pipelines.Conduct performance analysis and optimizationEvaluate memory and control requirementsDevelop design specs, register specsLead Verilog design and verification of MPEG decoder

 

Requirements MS or BSEE with 8+ years experience in specification, architecture, microarchitecture and implementation of MPEG video codec ASICs.Working knowledge of MPEG2/4, H.264, Windows Media and other video compression standards.Previously architected, designed and productized at least 2 MPEG codecs.Must be familiar with all stages of ASIC design flow including specification, performance simulation, Verilog design and simulation, DFT, synthesis, timing, floorplanning, ECO, bringup. Must have excellent Verilog coding and simulation skills, C/C++, Perl.Good communication, documentation and presentation skills.